A method of synchronization between high-speed DAC chips

Guoman Liu; Yang Lou; Meiguo Gao; Yiwei Shi

doi:10.1109/ICISE.2009.64

A method of synchronization between high-speed DAC chips

Guoman Liu^*, Yang Lou, Meiguo Gao, Yiwei Shi

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

An asynchronism problem between High-Speed DAC Chips in some multi-channel systems is analyzed. And, a method to solve this problem is proposed: Finding out the difference between clocks of each DAC, then compensating through data based on the difference in order to synchronize them. At the end, a diagram is proposed to solve the problem with this method in FPGA.

Original language	English
Title of host publication	2009 1st International Conference on Information Science and Engineering, ICISE 2009
Pages	451-453
Number of pages	3
DOIs	https://doi.org/10.1109/ICISE.2009.64
Publication status	Published - 2009
Event	1st International Conference on Information Science and Engineering, ICISE2009 - Nanjing, China Duration: 26 Dec 2009 → 28 Dec 2009

Publication series

Name	2009 1st International Conference on Information Science and Engineering, ICISE 2009

Conference

Conference	1st International Conference on Information Science and Engineering, ICISE2009
Country/Territory	China
City	Nanjing
Period	26/12/09 → 28/12/09

Keywords

High-Speed DAC
Synchronization

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10.1109/ICISE.2009.64

Cite this

@inproceedings{76e0f1f908ca4d289174720715465251,

title = "A method of synchronization between high-speed DAC chips",

abstract = "An asynchronism problem between High-Speed DAC Chips in some multi-channel systems is analyzed. And, a method to solve this problem is proposed: Finding out the difference between clocks of each DAC, then compensating through data based on the difference in order to synchronize them. At the end, a diagram is proposed to solve the problem with this method in FPGA.",

keywords = "High-Speed DAC, Synchronization",

author = "Guoman Liu and Yang Lou and Meiguo Gao and Yiwei Shi",

year = "2009",

doi = "10.1109/ICISE.2009.64",

language = "English",

isbn = "9780769538877",

series = "2009 1st International Conference on Information Science and Engineering, ICISE 2009",

pages = "451--453",

booktitle = "2009 1st International Conference on Information Science and Engineering, ICISE 2009",

note = "1st International Conference on Information Science and Engineering, ICISE2009 ; Conference date: 26-12-2009 Through 28-12-2009",

}

Liu, G, Lou, Y, Gao, M & Shi, Y 2009, A method of synchronization between high-speed DAC chips. in 2009 1st International Conference on Information Science and Engineering, ICISE 2009., 5454570, 2009 1st International Conference on Information Science and Engineering, ICISE 2009, pp. 451-453, 1st International Conference on Information Science and Engineering, ICISE2009, Nanjing, China, 26/12/09. https://doi.org/10.1109/ICISE.2009.64

A method of synchronization between high-speed DAC chips. / Liu, Guoman; Lou, Yang; Gao, Meiguo et al.
2009 1st International Conference on Information Science and Engineering, ICISE 2009. 2009. p. 451-453 5454570 (2009 1st International Conference on Information Science and Engineering, ICISE 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Liu, Guoman

AU - Lou, Yang

AU - Gao, Meiguo

AU - Shi, Yiwei

PY - 2009

Y1 - 2009

N2 - An asynchronism problem between High-Speed DAC Chips in some multi-channel systems is analyzed. And, a method to solve this problem is proposed: Finding out the difference between clocks of each DAC, then compensating through data based on the difference in order to synchronize them. At the end, a diagram is proposed to solve the problem with this method in FPGA.

AB - An asynchronism problem between High-Speed DAC Chips in some multi-channel systems is analyzed. And, a method to solve this problem is proposed: Finding out the difference between clocks of each DAC, then compensating through data based on the difference in order to synchronize them. At the end, a diagram is proposed to solve the problem with this method in FPGA.

KW - High-Speed DAC

KW - Synchronization

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U2 - 10.1109/ICISE.2009.64

DO - 10.1109/ICISE.2009.64

M3 - Conference contribution

AN - SCOPUS:77952762129

SN - 9780769538877

T3 - 2009 1st International Conference on Information Science and Engineering, ICISE 2009

SP - 451

EP - 453

BT - 2009 1st International Conference on Information Science and Engineering, ICISE 2009

T2 - 1st International Conference on Information Science and Engineering, ICISE2009

Y2 - 26 December 2009 through 28 December 2009

ER -

A method of synchronization between high-speed DAC chips

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Keywords

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