A joint implementation for bit synchronization and filtering in high-speed digital receivers

To deal with the problem of timing recovery in high-speed digital receivers, a joint implementation for bit synchronization and filtering is presented, which converts the signal to the frequency domain through the tool of fast Fourier transform (FFT). Therefore, the scheme could greatly depress not only the algorithm complexity but also the cost of hardware resources. In addition, the module could work stably prior to carrier synchronization. Both theory analysis and computer simulation show that this architecture has a low computational complexity, and could achieve the timing recovery accurately under a normal signal-to-noise condition (about 15 dB). Also there is probably 60% decrease of the computation in contrast to the arithmetic working in time domain. The presented module could be adapted to the high-speed demodulator.