TY - GEN
T1 - A highly efficient digital down converter in wide band digital radar receiver
AU - Pang, Long
AU - Zhu, Bocheng
AU - Chen, He
AU - Xie, Yizhuang
PY - 2012
Y1 - 2012
N2 - An improved design method for digital down converter (DDC) is proposed here to satisfy the increased requirements for miniaturization and low power consumption of signal processor in digital wide band radar receiver. Using the sampling technique that the sampling frequency equals to four times the intermediate frequency (IF) of echo signals, combining with the tap coefficient characteristics of half band finite impulse response (FIR) filter, a specific hardware structure is generated after detailed theoretical derivation. With this structure, the signal processing complexity and resource utilization are both reduced significantly, especially the multiplier blocks. Finally, compared with conventional design method, the design results based on FPGA show that the logical resources are saved by 83.65% and the power consumption is reduced by 110 mW, indicating the validity and good engineering applicability of this method.
AB - An improved design method for digital down converter (DDC) is proposed here to satisfy the increased requirements for miniaturization and low power consumption of signal processor in digital wide band radar receiver. Using the sampling technique that the sampling frequency equals to four times the intermediate frequency (IF) of echo signals, combining with the tap coefficient characteristics of half band finite impulse response (FIR) filter, a specific hardware structure is generated after detailed theoretical derivation. With this structure, the signal processing complexity and resource utilization are both reduced significantly, especially the multiplier blocks. Finally, compared with conventional design method, the design results based on FPGA show that the logical resources are saved by 83.65% and the power consumption is reduced by 110 mW, indicating the validity and good engineering applicability of this method.
KW - digital down converter (DDC)
KW - field programmable gate array (FPGA)
KW - finite impulse response (FIR)
KW - half band filter
KW - tap coefficients
UR - https://www.scopus.com/pages/publications/84876464406
U2 - 10.1109/ICoSP.2012.6491928
DO - 10.1109/ICoSP.2012.6491928
M3 - Conference contribution
AN - SCOPUS:84876464406
SN - 9781467321945
T3 - International Conference on Signal Processing Proceedings, ICSP
SP - 1795
EP - 1798
BT - ICSP 2012 - 2012 11th International Conference on Signal Processing, Proceedings
T2 - 2012 11th International Conference on Signal Processing, ICSP 2012
Y2 - 21 October 2012 through 25 October 2012
ER -