A High-Fidelity Two-Point Transmitter With Small-Sized Loop Filter and Low-Cost Quadrature Divider

Chen Wang; Yuyang Ding; Chunli Huang; Bo Zhou; Huikai Xie

doi:10.1109/LMWT.2025.3563611

A High-Fidelity Two-Point Transmitter With Small-Sized Loop Filter and Low-Cost Quadrature Divider

Chen Wang, Yuyang Ding, Chunli Huang, Bo Zhou^*, Huikai Xie

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

A full-integrated two-point transmitter with 1-Mb/s Gaussian-frequency-shift-keying (GFSK) modulation is fabricated in 65-nm CMOS. Both a small-sized loop filter (LF) based on cascaded capacitor multiplier and an ultralow-cost radio frequency (RF) quadrature divider based on cross-coupling self-biased tristate gates, are proposed, which are fully different from the existing designs. Various linearization mechanisms are utilized in the transmitter sub-modules to ensure high fidelity. Experimental results show that the presented work accomplishes an error vector magnitude (EVM) of 1.94%, an output power up to 1.9 dBm and the out-of-band phase noise (PN) of −124 dBc/Hz at 1-MHz offset frequency, with the power dissipation of 3.75 mW from a 1.2-V supply and an active area of 0.51

Original language	English
Journal	IEEE Microwave and Wireless Technology Letters
DOIs	https://doi.org/10.1109/LMWT.2025.3563611
Publication status	Accepted/In press - 2025

Keywords

Cascaded capacitor multiplier
linearization mechanism
radio frequency (RF) quadrature divider
two-point transmitter

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10.1109/LMWT.2025.3563611

Cite this

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title = "A High-Fidelity Two-Point Transmitter With Small-Sized Loop Filter and Low-Cost Quadrature Divider",

abstract = "A full-integrated two-point transmitter with 1-Mb/s Gaussian-frequency-shift-keying (GFSK) modulation is fabricated in 65-nm CMOS. Both a small-sized loop filter (LF) based on cascaded capacitor multiplier and an ultralow-cost radio frequency (RF) quadrature divider based on cross-coupling self-biased tristate gates, are proposed, which are fully different from the existing designs. Various linearization mechanisms are utilized in the transmitter sub-modules to ensure high fidelity. Experimental results show that the presented work accomplishes an error vector magnitude (EVM) of 1.94%, an output power up to 1.9 dBm and the out-of-band phase noise (PN) of −124 dBc/Hz at 1-MHz offset frequency, with the power dissipation of 3.75 mW from a 1.2-V supply and an active area of 0.51",

keywords = "Cascaded capacitor multiplier, linearization mechanism, radio frequency (RF) quadrature divider, two-point transmitter",

author = "Chen Wang and Yuyang Ding and Chunli Huang and Bo Zhou and Huikai Xie",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.",

year = "2025",

doi = "10.1109/LMWT.2025.3563611",

language = "English",

journal = "IEEE Microwave and Wireless Technology Letters",

issn = "2771-957X",

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T1 - A High-Fidelity Two-Point Transmitter With Small-Sized Loop Filter and Low-Cost Quadrature Divider

AU - Wang, Chen

AU - Ding, Yuyang

AU - Huang, Chunli

AU - Zhou, Bo

AU - Xie, Huikai

PY - 2025

Y1 - 2025

N2 - A full-integrated two-point transmitter with 1-Mb/s Gaussian-frequency-shift-keying (GFSK) modulation is fabricated in 65-nm CMOS. Both a small-sized loop filter (LF) based on cascaded capacitor multiplier and an ultralow-cost radio frequency (RF) quadrature divider based on cross-coupling self-biased tristate gates, are proposed, which are fully different from the existing designs. Various linearization mechanisms are utilized in the transmitter sub-modules to ensure high fidelity. Experimental results show that the presented work accomplishes an error vector magnitude (EVM) of 1.94%, an output power up to 1.9 dBm and the out-of-band phase noise (PN) of −124 dBc/Hz at 1-MHz offset frequency, with the power dissipation of 3.75 mW from a 1.2-V supply and an active area of 0.51

AB - A full-integrated two-point transmitter with 1-Mb/s Gaussian-frequency-shift-keying (GFSK) modulation is fabricated in 65-nm CMOS. Both a small-sized loop filter (LF) based on cascaded capacitor multiplier and an ultralow-cost radio frequency (RF) quadrature divider based on cross-coupling self-biased tristate gates, are proposed, which are fully different from the existing designs. Various linearization mechanisms are utilized in the transmitter sub-modules to ensure high fidelity. Experimental results show that the presented work accomplishes an error vector magnitude (EVM) of 1.94%, an output power up to 1.9 dBm and the out-of-band phase noise (PN) of −124 dBc/Hz at 1-MHz offset frequency, with the power dissipation of 3.75 mW from a 1.2-V supply and an active area of 0.51

KW - Cascaded capacitor multiplier

KW - linearization mechanism

KW - radio frequency (RF) quadrature divider

KW - two-point transmitter

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U2 - 10.1109/LMWT.2025.3563611

DO - 10.1109/LMWT.2025.3563611

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SN - 2771-957X

JO - IEEE Microwave and Wireless Technology Letters

JF - IEEE Microwave and Wireless Technology Letters

ER -

A High-Fidelity Two-Point Transmitter With Small-Sized Loop Filter and Low-Cost Quadrature Divider

Abstract

Keywords

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