TY - JOUR
T1 - A hardware-efficient parallel architecture for real-time blob analysis based on run-length code
AU - Li, Bingjie
AU - Zhang, Cunguang
AU - Li, Bo
AU - Jiang, Hongxu
AU - Xu, Qizhi
N1 - Publisher Copyright:
© 2017, Springer-Verlag GmbH Germany.
PY - 2018/10/1
Y1 - 2018/10/1
N2 - Blob analysis has been extensively used in target detection, object recognition, moving target tracking, among other applications. Because blob analysis is computationally expensive, it has become a bottleneck of real-time applications. To tackle this problem, a parallel algorithm for blob analysis is proposed, and a hardware-efficient architecture for this algorithm is presented in this paper. First, based on image data partition and multi-process units, a novel parallel algorithm of blob analysis is proposed to process objects with different types and sizes. Second, a dynamic convex hull calculation method is designed, which is highly efficient for parallel processing and sub-block merging of connected component labeling. Third, a parallel hardware structure of the proposed algorithm is designed and implemented on FPGA. To evaluate performance, blobs of different types and sizes are located by the proposed algorithm in software and hardware. The experimental results demonstrate that the blobs are effectively and correctly located by the proposed algorithm, and the proposed hardware architecture works more efficiently than the state-of-the-art methods.
AB - Blob analysis has been extensively used in target detection, object recognition, moving target tracking, among other applications. Because blob analysis is computationally expensive, it has become a bottleneck of real-time applications. To tackle this problem, a parallel algorithm for blob analysis is proposed, and a hardware-efficient architecture for this algorithm is presented in this paper. First, based on image data partition and multi-process units, a novel parallel algorithm of blob analysis is proposed to process objects with different types and sizes. Second, a dynamic convex hull calculation method is designed, which is highly efficient for parallel processing and sub-block merging of connected component labeling. Third, a parallel hardware structure of the proposed algorithm is designed and implemented on FPGA. To evaluate performance, blobs of different types and sizes are located by the proposed algorithm in software and hardware. The experimental results demonstrate that the blobs are effectively and correctly located by the proposed algorithm, and the proposed hardware architecture works more efficiently than the state-of-the-art methods.
KW - Blob analysis
KW - Convex hull calculation
KW - FPGA
KW - Parallelization
UR - http://www.scopus.com/inward/record.url?scp=85029586800&partnerID=8YFLogxK
U2 - 10.1007/s11554-017-0709-0
DO - 10.1007/s11554-017-0709-0
M3 - Article
AN - SCOPUS:85029586800
SN - 1861-8200
VL - 15
SP - 657
EP - 672
JO - Journal of Real-Time Image Processing
JF - Journal of Real-Time Image Processing
IS - 3
ER -