Abstract
As Internet of Things (IoT) systems transition toward post-quantum security, edge devices and gateways must perform authentication, firmware verification, and hash-tree signatures under strict latency constraints. These workloads require high-throughput Keccak hashing, particularly the numerous SHAKE256 calls in SLH-DSA-SHAKE. This paper presents a foldable fully-pipelined SHA-3 architecture that maps the 24 Keccak-f[1600] rounds onto configurable 24, 12, or 8-stage feed-forward pipelines. The pipelines require no feedback path, FSM-based round scheduling, or runtime round-constant control, and achieve an initiation interval of one cycle. The design supports SHA3-224/256/384/512. On Zynq UltraScale+, the 24-stage implementation reaches 460.8, 435.2, 332.8, and 230.4 Gbps, respectively. For SHA3-512, throughput and equivalent area efficiency improve by up to 20.89× and 9.89× over prior FPGA designs. The architecture is further extended with SHAKE256 configurations for SLH-DSA-SHAKE-128s/f and integrated into a complete SLH-DSA-SHAKE-128f accelerator. On Virtex-7, key generation, signing, and verification take 0.03, 0.66, and 0.12 ms, yielding latency speedups of up to 7.33×, 29.24×, and 15.92×, respectively. ASIC results across multiple technology nodes further confirm its high-throughput capability. These results demonstrate that the proposed architecture removes the Keccak round-serialization bottleneck and supports high-throughput post-quantum IoT security.
| Original language | English |
|---|---|
| Journal | IEEE Internet of Things Journal |
| DOIs | |
| Publication status | Accepted/In press - 2026 |
| Externally published | Yes |
Keywords
- ASIC
- fully-pipelined architecture
- hardware accelerator
- post-quantum cryptography
- SHA-3
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