A contamination-free and low-leakage-current Cu-TSV technology enabled by engineered double-sided processing

Through-silicon vias (TSVs) are crucial to the heterogeneous integration of multi-functional chiplets, providing high-performance vertical interconnects between different device layers. In this work, we introduce a novel TSV fabrication technology based on double-sided processing of polyimide-Ni (PI-Ni) functional layers, which can greatly simplify the TSV manufacturing flow, accompanying by advantages in improving TSV performance and reliability by effectively eliminating Cu contamination and significantly reducing leakage current. The key advancements of this approach include: (i) the complete coverage of the substrate with through-holes by the optimized double-sided PI insulation layer deposition process, where the chemical mechanical polishing (CMP) is carried out prior to the TSV metallization thus preventing substrate exposure to metallic contaminants; (ii) the deposition of a continuous Ni layer through an optimized double-sided electroless plating process, serving as both the barrier and the seed layer with high step coverage, enabling the simultaneous electroplating of TSV Cu conductors and double-sided redistribution layers (RDLs); and (iii) the demonstration of simulations and experimental validations highlighting improved thermo-mechanical stress distribution and superior electrical performance, including reduced parasitic capacitance and ultra-low leakage current. The engineered PI-Ni-based TSV fabrication technology offers a contamination-free Cu-interconnect solution for advanced post-Moore applications such as hetero-integrated microsystems containing IC chips and MEMS devices. (Figure presented.).