Abstract
In this work, a biological retina inspired tone mapping processor for high-speed and energy-efficient image enhancement has been proposed. To achieve high throughput and high energy efficiency, several hardware design techniques have been proposed, including data partition based parallel processing with S-shape sliding, adjacent frame feature sharing, multi-layer convolution pipelining, and convolution filter compression with zero skipping convolution. Implemented on a Xilinx’s Virtex7 FPGA, the proposed design achieves a high throughput of 189 frames per second for 1024 × 768 RGB images while consuming 819 mW. Compared with several state-of-the-art tone mapping processors, the proposed design shows higher throughput and energy efficiency. It is suitable for high-speed and energy-constrained image enhancement applications.
| Original language | English |
|---|---|
| Article number | 5600 |
| Pages (from-to) | 1-11 |
| Number of pages | 11 |
| Journal | Sensors |
| Volume | 20 |
| Issue number | 19 |
| DOIs | |
| Publication status | Published - 1 Oct 2020 |
| Externally published | Yes |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
Keywords
- Energy-efficient
- High throughput
- Retina
- Tone mapping processor
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