A 78.6 dB-SNDR 520mVpp-full-scale 620MΩ-Zin 105dBCMRR VCO-based Sensor Readout Circuit Using FVF-Based Gm-Input Structure

Classic sensor readout circuits generally consist of an instrumentation amplifier (IA) followed by an ADC. As emerging IoT and biomedical applications further tightening power and area budgets, direct-digitizing sensor readouts obviating the IA have drawn rising interest for their high power and area efficiency. Capacitor-coupling input network and capacitive feedback digital-to-analog converter (C-DAC) are used in some Delta Sigma ADCs to achieve wide DR and high energy efficiency [1]-[2]. However, the capacitive input network cannot provide high input impedance under chopping. Alternatively, some works [3]-[4] replace the capacitive input network with a transconductor (Gm) for high impedance. To improve linearity, [3] uses a resistive feedback DAC (R-DAC) to degenerate the transconductor and close the Delta Sigma loop. However, this method is not compatible with the dynamic element matching (DEM) technique and the R-DAC has to be large to reduce mismatch. Work [4] linearizes the transconductor by introducing two OTAs, which increases complexity and power consumption. And the OTAs are still large in area to suppress 1/f noise.