A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application

Chengying Chen; Liming Chen; Xinghua Wang; Feng Zhang

doi:10.1109/ISCAS.2018.8351783

A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application

Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang

School of Integrated Circuits and Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Citations (Scopus)

Abstract

For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2^nd Sigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8351783
Publication status	Published - 26 Apr 2018
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: 27 May 2018 → 30 May 2018

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2018-May
ISSN (Print)	0271-4310

Conference

Conference	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country/Territory	Italy
City	Florence
Period	27/05/18 → 30/05/18

Keywords

analog front-end
electrocardiogram
electroencephalogram
low noise
low power

Access to Document

10.1109/ISCAS.2018.8351783

Cite this

Chen, C., Chen, L., Wang, X., & Zhang, F. (2018). A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings Article 8351783 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351783

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title = "A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application",

abstract = "For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2nd Sigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.",

keywords = "analog front-end, electrocardiogram, electroencephalogram, low noise, low power",

author = "Chengying Chen and Liming Chen and Xinghua Wang and Feng Zhang",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

year = "2018",

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doi = "10.1109/ISCAS.2018.8351783",

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Chen, C, Chen, L, Wang, X & Zhang, F 2018, A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351783, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2018-May, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8351783

A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. / Chen, Chengying; Chen, Liming; Wang, Xinghua et al.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8351783 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application

AU - Chen, Chengying

AU - Chen, Liming

AU - Wang, Xinghua

AU - Zhang, Feng

PY - 2018/4/26

Y1 - 2018/4/26

N2 - For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2nd Sigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.

AB - For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2nd Sigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.

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A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application

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