A 5 Gbps serial link pre-emphasis transmitter with a novel-designed register based multiplexer

Xiaoran Li; Shunan Zhong; Fei Shi; Weijiang Wang

doi:10.1016/j.aeue.2017.05.033

A 5 Gbps serial link pre-emphasis transmitter with a novel-designed register based multiplexer

Xiaoran Li, Shunan Zhong, Fei Shi, Weijiang Wang^*

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

A serial link transmitter with 4-tap pre-emphasis is presented in this manuscript. The system consists of two 5:1 multiplexers, a 2:1CML multiplexer, and a driver with 4-tap pre-emphasis. A new 5:1 multiplexer structure is proposed to prevent sampling on the data edge, which shows a lower power consumption and chip size. Implement in standard 180 nm CMOS 1P6M process with 1.8 V power supply, the newly designed transmitter can be able to work with bit error rate (BER) as 10⁻¹⁴. The transmitter output jitter is 0.09UI while the amplitude can reach from 540 mV to 750 mV.

Original language	English
Pages (from-to)	184-191
Number of pages	8
Journal	AEU - International Journal of Electronics and Communications
Volume	79
DOIs	https://doi.org/10.1016/j.aeue.2017.05.033
Publication status	Published - Sept 2017

Keywords

BER
CMOS
Jitter
Pre-emphasis
Register based multiplexer
Transmitter

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10.1016/j.aeue.2017.05.033

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title = "A 5 Gbps serial link pre-emphasis transmitter with a novel-designed register based multiplexer",

abstract = "A serial link transmitter with 4-tap pre-emphasis is presented in this manuscript. The system consists of two 5:1 multiplexers, a 2:1CML multiplexer, and a driver with 4-tap pre-emphasis. A new 5:1 multiplexer structure is proposed to prevent sampling on the data edge, which shows a lower power consumption and chip size. Implement in standard 180 nm CMOS 1P6M process with 1.8 V power supply, the newly designed transmitter can be able to work with bit error rate (BER) as 10−14. The transmitter output jitter is 0.09UI while the amplitude can reach from 540 mV to 750 mV.",

keywords = "BER, CMOS, Jitter, Pre-emphasis, Register based multiplexer, Transmitter",

author = "Xiaoran Li and Shunan Zhong and Fei Shi and Weijiang Wang",

note = "Publisher Copyright: {\textcopyright} 2017 Elsevier GmbH",

year = "2017",

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language = "English",

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AU - Li, Xiaoran

AU - Zhong, Shunan

AU - Shi, Fei

AU - Wang, Weijiang

PY - 2017/9

Y1 - 2017/9

N2 - A serial link transmitter with 4-tap pre-emphasis is presented in this manuscript. The system consists of two 5:1 multiplexers, a 2:1CML multiplexer, and a driver with 4-tap pre-emphasis. A new 5:1 multiplexer structure is proposed to prevent sampling on the data edge, which shows a lower power consumption and chip size. Implement in standard 180 nm CMOS 1P6M process with 1.8 V power supply, the newly designed transmitter can be able to work with bit error rate (BER) as 10−14. The transmitter output jitter is 0.09UI while the amplitude can reach from 540 mV to 750 mV.

AB - A serial link transmitter with 4-tap pre-emphasis is presented in this manuscript. The system consists of two 5:1 multiplexers, a 2:1CML multiplexer, and a driver with 4-tap pre-emphasis. A new 5:1 multiplexer structure is proposed to prevent sampling on the data edge, which shows a lower power consumption and chip size. Implement in standard 180 nm CMOS 1P6M process with 1.8 V power supply, the newly designed transmitter can be able to work with bit error rate (BER) as 10−14. The transmitter output jitter is 0.09UI while the amplitude can reach from 540 mV to 750 mV.

KW - BER

KW - CMOS

KW - Jitter

KW - Pre-emphasis

KW - Register based multiplexer

KW - Transmitter

UR - https://www.scopus.com/pages/publications/85028605303

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DO - 10.1016/j.aeue.2017.05.033

M3 - Article

AN - SCOPUS:85028605303

SN - 1434-8411

VL - 79

SP - 184

EP - 191

JO - AEU - International Journal of Electronics and Communications

JF - AEU - International Journal of Electronics and Communications

ER -

A 5 Gbps serial link pre-emphasis transmitter with a novel-designed register based multiplexer

Abstract

Keywords

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