A 48 ps resolution, timing chip constructed from two expandable 32-channel register-only TDCs

Raman spectroscopy is a versatile, nondestructive, and label-free optical analysis technique. To effectively suppress the interference of fluorescence photons in gated-Raman spectroscopy applications, this work presents a novel timing chip featuring 48 ps resolution. The chip is constructed from two expandable 32-channel Time-to-Digital Converter (TDC) cores, resulting in a total of 64 channels. Each TDC core maintains a unified channel height of 30 μm, facilitating seamless integration with concurrent Single Photon Avalanche Diode (SPAD) technology. The proposed TDC architecture relies exclusively on standard digital gates—primarily D-type flip-flops for latching binary results, and therefore eliminates the need for delay-sensitive analog components when consisting the channel. This “register-only” design naturally ensures high uniformity across channels and offers significant flexibility for expansion; in the presented prototype, two identical core blocks are simply placed side-by-side to achieve the 64-channel configuration. The system's 48 ps resolution is determined by thirteen critical rising edges. Shared among all TDC channels, these critical edges are distributed via isolated, shielded paths to minimize noise coupling. The thirteen capacitance-interpolated delay elements, which generates the critical edges upon triggering, are physically isolated from the TDC channels and placed in close proximity to one another. This compact, independent placement further minimizes mismatch among various TDC channels. The measuring resolution of the proposed architecture is dynamically stabilized against Process, Voltage, and Temperature (PVT) variations by a two-stage nested Delay-Locked Loop (DLL). Fabricated using 180 nm CMOS technology, the prototype’s functionality has been fully validated. Under 1 MHz periodic input excitation, the chip demonstrates high energy efficiency with a power consumption of only 0.48 mW/channel at a 1.8 V supply voltage. Moreover, after a one-time calibration process, the system achieves excellent linearity. The measurement results indicate that Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are maintained under 0.7 LSB and 2.5 LSB across nearly all TDC channels (63/64), respectively.