TY - JOUR
T1 - A 2.5 GS/s 14-bit D/A converter with 8 to 1 MUX
AU - Zhang, Jun'an
AU - Li, Guangjun
AU - Zhang, Ruitao
AU - Fu, Dongbing
AU - Li, Jiaoxue
AU - Wei, Yafeng
AU - Yan, Bo
AU - Liu, Jun
AU - Li, Ruzhang
PY - 2016/3
Y1 - 2016/3
N2 - A 2.5 GS/s 14-bit D/A converter (DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a "5+9" segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT (process, source voltage and temperature) corner is also presented. The 8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a "5-31"decoder is used to improve the DAC's dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer (DDS) chip, and is implemented in a 0.18 μm CMOS technology, occupies 4.86 × 2. 28 mm2 including bond pads (DAC only), and the measured performance is SFDR > 40 dB (with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure (means return-to-zero or quad-switch structure is unutilized), this paper DAC's clock frequency (2.5 GHz) and higher output frequency SFDR (> 40 dB, up to 1 GHz) has some competition.
AB - A 2.5 GS/s 14-bit D/A converter (DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a "5+9" segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT (process, source voltage and temperature) corner is also presented. The 8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a "5-31"decoder is used to improve the DAC's dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer (DDS) chip, and is implemented in a 0.18 μm CMOS technology, occupies 4.86 × 2. 28 mm2 including bond pads (DAC only), and the measured performance is SFDR > 40 dB (with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure (means return-to-zero or quad-switch structure is unutilized), this paper DAC's clock frequency (2.5 GHz) and higher output frequency SFDR (> 40 dB, up to 1 GHz) has some competition.
KW - Bias circuit
KW - Dynamic element match (DEM)
KW - High speed MUX
KW - PMOS current-steering D/A converter
UR - http://www.scopus.com/inward/record.url?scp=84994589025&partnerID=8YFLogxK
U2 - 10.1088/1674-4926/37/3/035004
DO - 10.1088/1674-4926/37/3/035004
M3 - Article
AN - SCOPUS:84994589025
SN - 1674-4926
VL - 37
JO - Journal of Semiconductors
JF - Journal of Semiconductors
IS - 3
M1 - 035004
ER -