A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators

Time-interleaved (TI) SARs are popular choices for high-speed ADCs due to their high energy efficiency and scaling compatibility, but they suffer from timing skew that severely degrades the linearity. The key to the background calibration of the timing skew error Δt is to correctly estimate its sign, so that Δt can be minimized by adjusting a variable delay line. One way to estimate sgn(Δt) is to add a reference ADC channel (ref-ADC) and compare its output D_ref with each sub-ADC channel output D_i to obtain ΔV_in=D_i-D_ref. However, without knowing the input derivative dV_in/dt, the estimation of sgn(Δt) relies on computing auto-correlation or variance, which takes millions or even billions of samples to converge [1]. Thus, it is preferred to extract both Δ V_in and dV_in/dt, which allows the direct solving of sgn(Δt)=sgn(Δ V_in · d V_in/dt) and achieves a fast convergence. The derivative can be estimated by using a digital FIR filter, but it is computationally intensive and limits the input bandwidth [2]. It can also be extracted by adding another channel to build an analog derivative filter [3] [4]. This approach supports wide input bandwidth, but two extra channels result in large area and power overhead. To minimize the cost, this paper proposes a novel timing-skew calibration technique that uses only one extra channel to extract both ΔV_in and dV_in/dt, achieving low-cost and fast calibration. Dummy loads are used to compensate the impedance modulation effect. This paper also proposes a novel variable-load comparator. It outperforms the conventional design in both speed and energy efficiency. Equipped with the proposed calibration technique and comparators, a prototype 1.2GS/s 11b TI SAR ADC with an on-chip timing-skew calibration engine achieves 58.4 dB SNDR while consuming only 4.6 mW, leading to a competitive FoMs of 169.6 dB and FoMw of 5.6fJ/conv-step.