A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration

The pipelined ADC is an attractive choice for high-speed and high-resolution applications. Its most important building block is the residue amplifier. Compared with conventional closed-loop amplifiers, open-loop amplifiers are advantageous in speed, energy efficiency, design simplicity, and scaling friendliness [1]. However, they suffer from large gain errors and severe gain nonlinearity. Addressing these nonidealities conventionally requires polynomial-based calibration [1]-[3]. Although the calibration coefficients can be easily extracted in the background through dither injection and gated LMS filters [3], the polynomial computation introduces significant power and area overhead, especially at sampling rates over 1GS/s. The piecewise-linear (PWL) nonlinearity calibration scheme is an attractive alternative to reduce the computational complexity [4]. However, existing PWL calibration techniques extract the calibration coefficients in the foreground with large analog circuitry overhead [4] or in a queue scheme that limits the sampling rate [5]. To overcome these challenges, this paper proposes a novel PWL nonlinearity calibration technique that digitally extracts the calibration coefficients in the background through gated LMS filters with adaptive thresholds. A dual-path amplification scheme is also proposed to improve power efficiency and settling accuracy. Using these techniques, a prototype 12b 3GS/s pipelined ADC achieves a 58.8dB SNDR with a 1.5GHz input and consumes 32.5mW with an on-chip background calibration engine. This corresponds to an FoMS of 165dB and an FoMW of 15.2fJ/conv-step.