@inproceedings{c2634963682b44a48520ce91df91e44e,
title = "A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors",
abstract = "This work proposes a novel correlation-based digital background calibration algorithm that altogether calibrates the inter-stage gain, capacitor mismatch, and kick-back errors with low hardware overhead and simple control logic. A prototype 12b1GS/s pipelined ADC equipped with the proposed calibration technique achieves >60dB SNDR and >80dB SFDR across the entire Nyquist zone.",
keywords = "analog-to-digital converter (ADC), background calibration, capacitor mismatch, inter-stage gain, kick-back, pipelined ADC",
author = "Mingyang Gu and Yi Zhong and Lu Jie and Nan Sun",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 ; Conference date: 11-09-2023 Through 14-09-2023",
year = "2023",
doi = "10.1109/ESSCIRC59616.2023.10268748",
language = "English",
series = "European Solid-State Circuits Conference",
publisher = "IEEE Computer Society",
pages = "329--332",
booktitle = "ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference",
address = "United States",
}