A 12-b 3-GS/s Pipelined ADC With Piecewise-Linear Gain Nonlinearity Calibration

Mingyang Gu; Yi Zhong; Lu Jie; Nan Sun

doi:10.1109/OJSSCS.2026.3656850

A 12-b 3-GS/s Pipelined ADC With Piecewise-Linear Gain Nonlinearity Calibration

Mingyang Gu
, Yi Zhong
, Lu Jie
, Nan Sun^*

^*Corresponding author for this work

Tsinghua University

Research output: Contribution to journal › Article › peer-review

Abstract

This article presents a novel piecewise-linear gain nonlinearity calibration technique with low computational complexity and background coefficient extraction, enabling the use of open-loop amplifiers in pipelined ADCs for high energy efficiency. In addition to the gain nonlinearity calibration, circuit innovations such as a dual-path amplification scheme and a high-speed flash comparator are also introduced. Incorporating these techniques, a prototype 12-b 3-GS/s pipelined ADC is fabricated in a 28-nm CMOS process. Including the on-chip calibration engine, it consumes 50.5 mW and achieves an SNDR of 58.8 dB with a 1.5-GHz input, corresponding to a competitive FoMS of 164 dB.

Original language	English
Journal	IEEE Open Journal of the Solid-State Circuits Society
DOIs	https://doi.org/10.1109/OJSSCS.2026.3656850
Publication status	Accepted/In press - 2026
Externally published	Yes

Keywords

Analog-to-digital converter (ADC)
background calibration
gain nonlinearity calibration
open-loop amplifier
piecewise linear (PWL)
pipelined ADC

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10.1109/OJSSCS.2026.3656850

Cite this

@article{bca308aff6ea49e08fc9956ba33d84f7,

title = "A 12-b 3-GS/s Pipelined ADC With Piecewise-Linear Gain Nonlinearity Calibration",

abstract = "This article presents a novel piecewise-linear gain nonlinearity calibration technique with low computational complexity and background coefficient extraction, enabling the use of open-loop amplifiers in pipelined ADCs for high energy efficiency. In addition to the gain nonlinearity calibration, circuit innovations such as a dual-path amplification scheme and a high-speed flash comparator are also introduced. Incorporating these techniques, a prototype 12-b 3-GS/s pipelined ADC is fabricated in a 28-nm CMOS process. Including the on-chip calibration engine, it consumes 50.5 mW and achieves an SNDR of 58.8 dB with a 1.5-GHz input, corresponding to a competitive FoMS of 164 dB.",

keywords = "Analog-to-digital converter (ADC), background calibration, gain nonlinearity calibration, open-loop amplifier, piecewise linear (PWL), pipelined ADC",

author = "Mingyang Gu and Yi Zhong and Lu Jie and Nan Sun",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.",

year = "2026",

doi = "10.1109/OJSSCS.2026.3656850",

language = "English",

journal = "IEEE Open Journal of the Solid-State Circuits Society",

issn = "2644-1349",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - A 12-b 3-GS/s Pipelined ADC With Piecewise-Linear Gain Nonlinearity Calibration

AU - Gu, Mingyang

AU - Zhong, Yi

AU - Jie, Lu

AU - Sun, Nan

PY - 2026

Y1 - 2026

N2 - This article presents a novel piecewise-linear gain nonlinearity calibration technique with low computational complexity and background coefficient extraction, enabling the use of open-loop amplifiers in pipelined ADCs for high energy efficiency. In addition to the gain nonlinearity calibration, circuit innovations such as a dual-path amplification scheme and a high-speed flash comparator are also introduced. Incorporating these techniques, a prototype 12-b 3-GS/s pipelined ADC is fabricated in a 28-nm CMOS process. Including the on-chip calibration engine, it consumes 50.5 mW and achieves an SNDR of 58.8 dB with a 1.5-GHz input, corresponding to a competitive FoMS of 164 dB.

AB - This article presents a novel piecewise-linear gain nonlinearity calibration technique with low computational complexity and background coefficient extraction, enabling the use of open-loop amplifiers in pipelined ADCs for high energy efficiency. In addition to the gain nonlinearity calibration, circuit innovations such as a dual-path amplification scheme and a high-speed flash comparator are also introduced. Incorporating these techniques, a prototype 12-b 3-GS/s pipelined ADC is fabricated in a 28-nm CMOS process. Including the on-chip calibration engine, it consumes 50.5 mW and achieves an SNDR of 58.8 dB with a 1.5-GHz input, corresponding to a competitive FoMS of 164 dB.

KW - Analog-to-digital converter (ADC)

KW - background calibration

KW - gain nonlinearity calibration

KW - open-loop amplifier

KW - piecewise linear (PWL)

KW - pipelined ADC

UR - https://www.scopus.com/pages/publications/105028585092

U2 - 10.1109/OJSSCS.2026.3656850

DO - 10.1109/OJSSCS.2026.3656850

M3 - Article

AN - SCOPUS:105028585092

SN - 2644-1349

JO - IEEE Open Journal of the Solid-State Circuits Society

JF - IEEE Open Journal of the Solid-State Circuits Society

ER -

A 12-b 3-GS/s Pipelined ADC With Piecewise-Linear Gain Nonlinearity Calibration

Abstract

Keywords

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