A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation

Liyang Guo; Maodong Wang; Xiaojie Zhang; Xinghua Wang

doi:10.1109/IAEAC.2017.8054481

A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation

Liyang Guo, Maodong Wang, Xiaojie Zhang, Xinghua Wang

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

A 10bit 40MS/s asynchronous timing logic successive approximation analog-to-digital converter (SAR ADC) is presented, including a bootstrapped switch, a charge redistribution digital-to-analog converter(DAC) and a dynamic comparator. A redundancy compensation and a mismatch calibration are introduced to achieve conversion accuracy improvement. A monotonic capacitor switching technique is adopted to reduce the power consumption during conversion. The design of ADC was based on SMIC 0.18μm CMOS process and consumes 5.4mA at 1.8 V power supply. The SAR ADC exhibits an SNR and SFDR of 60.27dB and 65.58dB, respectively.

Original language	English
Title of host publication	Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017
Editors	Bing Xu
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2536-2540
Number of pages	5
ISBN (Electronic)	9781467389778
DOIs	https://doi.org/10.1109/IAEAC.2017.8054481
Publication status	Published - 29 Sept 2017
Event	2nd IEEE Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017 - Chongqing, China Duration: 25 Mar 2017 → 26 Mar 2017

Publication series

Name	Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017

Conference

Conference	2nd IEEE Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017
Country/Territory	China
City	Chongqing
Period	25/03/17 → 26/03/17

Keywords

Asynchronous timing logic
Mismatch calibration
Monotonic capacitor switching
Redundancy compensation
SAR ADC

Access to Document

10.1109/IAEAC.2017.8054481

Cite this

Guo, L., Wang, M., Zhang, X., & Wang, X. (2017). A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation. In B. Xu (Ed.), Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017 (pp. 2536-2540). Article 8054481 (Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IAEAC.2017.8054481

Guo, Liyang ; Wang, Maodong ; Zhang, Xiaojie et al. / A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation. Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017. editor / Bing Xu. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 2536-2540 (Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017).

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title = "A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation",

abstract = "A 10bit 40MS/s asynchronous timing logic successive approximation analog-to-digital converter (SAR ADC) is presented, including a bootstrapped switch, a charge redistribution digital-to-analog converter(DAC) and a dynamic comparator. A redundancy compensation and a mismatch calibration are introduced to achieve conversion accuracy improvement. A monotonic capacitor switching technique is adopted to reduce the power consumption during conversion. The design of ADC was based on SMIC 0.18μm CMOS process and consumes 5.4mA at 1.8 V power supply. The SAR ADC exhibits an SNR and SFDR of 60.27dB and 65.58dB, respectively.",

keywords = "Asynchronous timing logic, Mismatch calibration, Monotonic capacitor switching, Redundancy compensation, SAR ADC",

author = "Liyang Guo and Maodong Wang and Xiaojie Zhang and Xinghua Wang",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2nd IEEE Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017 ; Conference date: 25-03-2017 Through 26-03-2017",

year = "2017",

month = sep,

day = "29",

doi = "10.1109/IAEAC.2017.8054481",

language = "English",

series = "Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "2536--2540",

editor = "Bing Xu",

booktitle = "Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017",

address = "United States",

}

Guo, L, Wang, M, Zhang, X & Wang, X 2017, A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation. in B Xu (ed.), Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017., 8054481, Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 2536-2540, 2nd IEEE Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017, Chongqing, China, 25/03/17. https://doi.org/10.1109/IAEAC.2017.8054481

A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation. / Guo, Liyang; Wang, Maodong; Zhang, Xiaojie et al.
Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017. ed. / Bing Xu. Institute of Electrical and Electronics Engineers Inc., 2017. p. 2536-2540 8054481 (Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation

AU - Guo, Liyang

AU - Wang, Maodong

AU - Zhang, Xiaojie

AU - Wang, Xinghua

PY - 2017/9/29

Y1 - 2017/9/29

N2 - A 10bit 40MS/s asynchronous timing logic successive approximation analog-to-digital converter (SAR ADC) is presented, including a bootstrapped switch, a charge redistribution digital-to-analog converter(DAC) and a dynamic comparator. A redundancy compensation and a mismatch calibration are introduced to achieve conversion accuracy improvement. A monotonic capacitor switching technique is adopted to reduce the power consumption during conversion. The design of ADC was based on SMIC 0.18μm CMOS process and consumes 5.4mA at 1.8 V power supply. The SAR ADC exhibits an SNR and SFDR of 60.27dB and 65.58dB, respectively.

AB - A 10bit 40MS/s asynchronous timing logic successive approximation analog-to-digital converter (SAR ADC) is presented, including a bootstrapped switch, a charge redistribution digital-to-analog converter(DAC) and a dynamic comparator. A redundancy compensation and a mismatch calibration are introduced to achieve conversion accuracy improvement. A monotonic capacitor switching technique is adopted to reduce the power consumption during conversion. The design of ADC was based on SMIC 0.18μm CMOS process and consumes 5.4mA at 1.8 V power supply. The SAR ADC exhibits an SNR and SFDR of 60.27dB and 65.58dB, respectively.

KW - Asynchronous timing logic

KW - Mismatch calibration

KW - Monotonic capacitor switching

KW - Redundancy compensation

KW - SAR ADC

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BT - Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd IEEE Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017

Y2 - 25 March 2017 through 26 March 2017

ER -

Guo L, Wang M, Zhang X, Wang X. A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation. In Xu B, editor, Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 2536-2540. 8054481. (Proceedings of 2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2017). doi: 10.1109/IAEAC.2017.8054481

A 10bit 40MS/s SAR ADC in 0.18μm CMOS with redundancy compensation

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