A 100MHz Digital Down Converter with modified FIR filter for wideband Software-Defined Radios

Hua Ming Liu*, Guang Jun Li, Bo Yan, Qiang Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Citations (Scopus)

Abstract

Digital Down Converter is one of the key technologies in Software Defined Radio. In Digital Down Converter how to realize a high-speed, high-order FIR filter is an interesting problem. This paper proposes a modified Distributed Arithmetic, in which speed is improved and memory is saved compared with the traditional Distributed Arithmetic. The presented FIR filter based on the modified Distributed Arithmetic has been implemented in the form of ASIC which was fabricated in a SMIC 0.13μm CMOS process. The chip's sample rate can reach 10MSPS in the 80MHz system clock.

Original languageEnglish
Title of host publicationICEIE 2010 - 2010 International Conference on Electronics and Information Engineering, Proceedings
PagesV2540-V2544
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 International Conference on Electronics and Information Engineering, ICEIE 2010 - Kyoto, Japan
Duration: 1 Aug 20103 Aug 2010

Publication series

NameICEIE 2010 - 2010 International Conference on Electronics and Information Engineering, Proceedings
Volume2

Conference

Conference2010 International Conference on Electronics and Information Engineering, ICEIE 2010
Country/TerritoryJapan
CityKyoto
Period1/08/103/08/10

Keywords

  • DDC
  • FIR filter
  • Modified distributed arithmetic

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