A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer

Jianhua Lu; Zhigong Wang; Lei Tian; Rui Tao; Haitao Chen; Tingting Xie; Zhiheng Chen; Jun Feng; Yi Dong; Shizhong Xie

doi:10.1109/ICCCAS.2002.1180739

A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer

Jianhua Lu^*
, Zhigong Wang
, Lei Tian
, Rui Tao
, Haitao Chen
, Tingting Xie
, Zhiheng Chen
, Jun Feng
, Yi Dong
, Shizhong Xie

^*Corresponding author for this work

Southeast University, Nanjing
Tsinghua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

A 4.8 Gbit/s 4:1 multiplexer was designed in source coupled logic and fabricated in 0.35 μm CMOS technology. It has a power dissipation of less than 1W from a 5V supply and a size of 1×1.05 mm², and can be directly applied to an optical fiber link at STM-16 (2.488 Gbit/s) level of synchronous digital hierarchy (SDH).

Original language	English
Title of host publication	2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings
Editors	Lemin Li
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	824-826
Number of pages	3
ISBN (Electronic)	0780375475, 9780780375475
DOIs	https://doi.org/10.1109/ICCCAS.2002.1180739
Publication status	Published - 2002
Externally published	Yes
Event	1st International Conference on Communications, Circuits and Systems, ICCCAS 2002 - Chengdu, China Duration: 29 Jun 2002 → 1 Jul 2002

Publication series

Name	2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings

Conference

Conference	1st International Conference on Communications, Circuits and Systems, ICCCAS 2002
Country/Territory	China
City	Chengdu
Period	29/06/02 → 1/07/02

Keywords

CMOS
Multiplexer
SDH
STM-16

Access to Document

10.1109/ICCCAS.2002.1180739

Cite this

Lu, J., Wang, Z., Tian, L., Tao, R., Chen, H., Xie, T., Chen, Z., Feng, J., Dong, Y., & Xie, S. (2002). A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer. In L. Li (Ed.), 2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings (pp. 824-826). Article 1180739 (2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCCAS.2002.1180739

Lu, Jianhua ; Wang, Zhigong ; Tian, Lei et al. / A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer. 2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings. editor / Lemin Li. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 824-826 (2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings).

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title = "A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer",

abstract = "A 4.8 Gbit/s 4:1 multiplexer was designed in source coupled logic and fabricated in 0.35 μm CMOS technology. It has a power dissipation of less than 1W from a 5V supply and a size of 1×1.05 mm2, and can be directly applied to an optical fiber link at STM-16 (2.488 Gbit/s) level of synchronous digital hierarchy (SDH).",

keywords = "CMOS, Multiplexer, SDH, STM-16",

author = "Jianhua Lu and Zhigong Wang and Lei Tian and Rui Tao and Haitao Chen and Tingting Xie and Zhiheng Chen and Jun Feng and Yi Dong and Shizhong Xie",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 1st International Conference on Communications, Circuits and Systems, ICCCAS 2002 ; Conference date: 29-06-2002 Through 01-07-2002",

year = "2002",

doi = "10.1109/ICCCAS.2002.1180739",

language = "English",

series = "2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "824--826",

editor = "Lemin Li",

booktitle = "2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings",

address = "United States",

}

Lu, J, Wang, Z, Tian, L, Tao, R, Chen, H, Xie, T, Chen, Z, Feng, J, Dong, Y & Xie, S 2002, A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer. in L Li (ed.), 2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings., 1180739, 2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 824-826, 1st International Conference on Communications, Circuits and Systems, ICCCAS 2002, Chengdu, China, 29/06/02. https://doi.org/10.1109/ICCCAS.2002.1180739

A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer. / Lu, Jianhua; Wang, Zhigong; Tian, Lei et al.
2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings. ed. / Lemin Li. Institute of Electrical and Electronics Engineers Inc., 2002. p. 824-826 1180739 (2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer

AU - Lu, Jianhua

AU - Wang, Zhigong

AU - Tian, Lei

AU - Tao, Rui

AU - Chen, Haitao

AU - Xie, Tingting

AU - Chen, Zhiheng

AU - Feng, Jun

AU - Dong, Yi

AU - Xie, Shizhong

PY - 2002

Y1 - 2002

N2 - A 4.8 Gbit/s 4:1 multiplexer was designed in source coupled logic and fabricated in 0.35 μm CMOS technology. It has a power dissipation of less than 1W from a 5V supply and a size of 1×1.05 mm2, and can be directly applied to an optical fiber link at STM-16 (2.488 Gbit/s) level of synchronous digital hierarchy (SDH).

AB - A 4.8 Gbit/s 4:1 multiplexer was designed in source coupled logic and fabricated in 0.35 μm CMOS technology. It has a power dissipation of less than 1W from a 5V supply and a size of 1×1.05 mm2, and can be directly applied to an optical fiber link at STM-16 (2.488 Gbit/s) level of synchronous digital hierarchy (SDH).

KW - CMOS

KW - Multiplexer

KW - SDH

KW - STM-16

UR - https://www.scopus.com/pages/publications/84969677985

U2 - 10.1109/ICCCAS.2002.1180739

DO - 10.1109/ICCCAS.2002.1180739

M3 - Conference contribution

AN - SCOPUS:84969677985

T3 - 2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings

SP - 824

EP - 826

BT - 2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings

A2 - Li, Lemin

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st International Conference on Communications, Circuits and Systems, ICCCAS 2002

Y2 - 29 June 2002 through 1 July 2002

ER -

Lu J, Wang Z, Tian L, Tao R, Chen H, Xie T et al. A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer. In Li L, editor, 2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2002. p. 824-826. 1180739. (2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings). doi: 10.1109/ICCCAS.2002.1180739

A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer

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