A 0.021mm292dB-SNDR 88kHz-BW Incremental Zoom ADC with 2nd-order RT-DEM and Quiet Chopping

Chaoyang Xing; Yi Zhong; Nan Sun; Lu Jie

doi:10.1109/ESSCIRC59616.2023.10268741

A 0.021mm²92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2^nd-order RT-DEM and Quiet Chopping

Chaoyang Xing^*
, Yi Zhong
, Nan Sun
, Lu Jie

^*Corresponding author for this work

Tsinghua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

This work proposes a continuous-time incremental zoom ADC with an on-chip 2 n d -order decimation filter. It adopts a 2 n d -order RT-DEM technique to eliminate DAC mismatch with a customized bidirectional circular shift register, and the quiet chopping technique to achieve high input impedance. The prototype ADC presents 91.6dB SNDR over an 88kHz bandwidth, consuming only 437 μ W of power.

Original language	English
Title of host publication	ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference
Publisher	IEEE Computer Society
Pages	293-296
Number of pages	4
ISBN (Electronic)	9798350304206
DOIs	https://doi.org/10.1109/ESSCIRC59616.2023.10268741
Publication status	Published - 2023
Externally published	Yes
Event	49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 - Lisbon, Portugal Duration: 11 Sept 2023 → 14 Sept 2023

Publication series

Name	European Solid-State Circuits Conference
Volume	2023-September
ISSN (Print)	1930-8833

Conference

Conference	49th IEEE European Solid State Circuits Conference, ESSCIRC 2023
Country/Territory	Portugal
City	Lisbon
Period	11/09/23 → 14/09/23

Keywords

Continuous-time delta-sigma modulator (CTDSM)
Quiet chopping
Real-time dynamic element matching (RT-DEM)

Access to Document

10.1109/ESSCIRC59616.2023.10268741

Cite this

@inproceedings{47bc7a8e56204e78a0fb01c4954e726f,

title = "A 0.021mm292dB-SNDR 88kHz-BW Incremental Zoom ADC with 2nd-order RT-DEM and Quiet Chopping",

abstract = "This work proposes a continuous-time incremental zoom ADC with an on-chip 2 n d -order decimation filter. It adopts a 2 n d -order RT-DEM technique to eliminate DAC mismatch with a customized bidirectional circular shift register, and the quiet chopping technique to achieve high input impedance. The prototype ADC presents 91.6dB SNDR over an 88kHz bandwidth, consuming only 437 μ W of power.",

keywords = "Continuous-time delta-sigma modulator (CTDSM), Quiet chopping, Real-time dynamic element matching (RT-DEM)",

author = "Chaoyang Xing and Yi Zhong and Nan Sun and Lu Jie",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 ; Conference date: 11-09-2023 Through 14-09-2023",

year = "2023",

doi = "10.1109/ESSCIRC59616.2023.10268741",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "293--296",

booktitle = "ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference",

address = "United States",

}

Xing, C, Zhong, Y, Sun, N & Jie, L 2023, A 0.021mm²92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2^nd-order RT-DEM and Quiet Chopping. in ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference. European Solid-State Circuits Conference, vol. 2023-September, IEEE Computer Society, pp. 293-296, 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, 11/09/23. https://doi.org/10.1109/ESSCIRC59616.2023.10268741

A 0.021mm²92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2^nd-order RT-DEM and Quiet Chopping. / Xing, Chaoyang; Zhong, Yi; Sun, Nan et al.
ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference. IEEE Computer Society, 2023. p. 293-296 (European Solid-State Circuits Conference; Vol. 2023-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This work proposes a continuous-time incremental zoom ADC with an on-chip 2 n d -order decimation filter. It adopts a 2 n d -order RT-DEM technique to eliminate DAC mismatch with a customized bidirectional circular shift register, and the quiet chopping technique to achieve high input impedance. The prototype ADC presents 91.6dB SNDR over an 88kHz bandwidth, consuming only 437 μ W of power.

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