TY - GEN
T1 - 9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs
AU - He, Xiyu
AU - Gu, Mingyang
AU - Jiang, Hanjun
AU - Zhong, Yi
AU - Sun, Nan
AU - Jie, Lu
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Wideband (BW >100MHz) and high-dynamic-range (DR >70dB) ADCs are in high demand for next-generation wireless standards. Conventional ADC solutions face challenges in both performance and efficiency: CTDSMs demonstrate favorable DR within moderate bandwidths, but their design complexity escalates significantly when addressing wider BW due to their closed-loop nature. Conventional pipeline ADCs can achieve high BW and resolution, but this comes at the expense of high power consumption caused by the inter-stage amplifiers. The hybrid architecture of the pipe-SAR presents an appealing combination of high resolution and improved efficiency by taking advantage of the SAR architecture, which makes them well-suited for mobile devices. Nonetheless, the conversion rate of the pipe-SAR ADC remains restricted. To solve this challenge, this work presents an interleaved pipe-SAR architecture with a shared residue integrating amplifier. It improves the opamp efficiency by eliminating the reset phase in conventional residue amplifiers (RA) and provides 1st-order noise shaping to utilize the mandatory OSR from the anti-aliasing filter. The prototype ADC achieves 71.2dB SNDR over a 200MHz BW and consumes only 12.5mW, converting to a Schreier FoM of 173.2dB.
AB - Wideband (BW >100MHz) and high-dynamic-range (DR >70dB) ADCs are in high demand for next-generation wireless standards. Conventional ADC solutions face challenges in both performance and efficiency: CTDSMs demonstrate favorable DR within moderate bandwidths, but their design complexity escalates significantly when addressing wider BW due to their closed-loop nature. Conventional pipeline ADCs can achieve high BW and resolution, but this comes at the expense of high power consumption caused by the inter-stage amplifiers. The hybrid architecture of the pipe-SAR presents an appealing combination of high resolution and improved efficiency by taking advantage of the SAR architecture, which makes them well-suited for mobile devices. Nonetheless, the conversion rate of the pipe-SAR ADC remains restricted. To solve this challenge, this work presents an interleaved pipe-SAR architecture with a shared residue integrating amplifier. It improves the opamp efficiency by eliminating the reset phase in conventional residue amplifiers (RA) and provides 1st-order noise shaping to utilize the mandatory OSR from the anti-aliasing filter. The prototype ADC achieves 71.2dB SNDR over a 200MHz BW and consumes only 12.5mW, converting to a Schreier FoM of 173.2dB.
UR - https://www.scopus.com/pages/publications/85188115788
U2 - 10.1109/ISSCC49657.2024.10454431
DO - 10.1109/ISSCC49657.2024.10454431
M3 - Conference contribution
AN - SCOPUS:85188115788
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 172
EP - 174
BT - 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
Y2 - 18 February 2024 through 22 February 2024
ER -