8.5 GHz 1:8 frequency divider in 0.35 μm CMOS technology

An 1:8 frequency divider was designed and realized in a 0.35 μm standard CMOS technology. The chip consists of three stages of 1 : 2 divider cells, which are constructed with source couple logic (SCL) flip-flops. By revising the traditional topology of SCL flip-flop, a divider with better performance was obtained. The results of measurement show that the whole chip achieves the frequency division at more than 8.5 GHz. Each 1 : 2 cell divider cell consumes about 11 mW from a 3.3 V supply. The divider can be used in RF and optical-fiber transceivers and other high-speed systems.