@inproceedings{c5ac1e4363814a29a52d4405018f2e5a,
title = "2-Bit Quantizated CNN Accelerator on FPGA",
abstract = "In recent years, neural networks have seen extensive applications across various fields due to their high accuracy and ease of use. However, the computational demands of neural networks are extraordinarily high, making it challenging to meet real-time requirements in resource-constrained scenarios. To address this issue, this paper applies a neural network training algorithm that quantizes the neural network to a 2-bit precision without significantly affecting its accuracy. To further improve the real-time performance of the neural network, a dedicated computational unit is designed for it. The proposed neural network accelerator includes a learnable threshold non-uniform quantization module, a 2-bit neural network multiplier unit, and a convolution quantization fusion module. On the Xilinx MPSoC ZU2EG chip, the accelerator achieves a peak performance of 512 GOPS while utilizing only 18,597 LUTs.",
keywords = "component, FPGA implementation, neural network, quantization",
author = "Boyu Zhu and Yanjun Zhang and Xu Yang and Gongyu Fan and Jingyi Chen and Yuteng Cao and Chongchang Xu and Yongxiang Zhou",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 5th International Conference on Neural Networks, Information and Communication Engineering, NNICE 2025 ; Conference date: 10-01-2025 Through 12-01-2025",
year = "2025",
doi = "10.1109/NNICE64954.2025.11064319",
language = "English",
series = "2025 5th International Conference on Neural Networks, Information and Communication Engineering, NNICE 2025",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1297--1300",
booktitle = "2025 5th International Conference on Neural Networks, Information and Communication Engineering, NNICE 2025",
address = "United States",
}