Abstract
A multi-modulus-divider (MMD) was designed based on TSMC 90 nm CMOS process, achieving a division range of the MMD from 32 to 39. The block diagram of MMD, including double-modulus-divider, S counter and P counter were discussed in detail. Time sequence requirement of the P counters with and without retime circuit were analyzed and discussed. The proposed MMD was integrated into a K-band fractional-N frequency synthesizer. The measurement results show that in-band phase noise performance can be optimized about 15 dB through the modified MMD. The measurement results exhibit the phase noise performance can achieve -81.3 dBc/Hz and -72.44 dBc/Hz at 10 kHz frequency offset and 1 kHz frequency offset, respectively.
| Translated title of the contribution | Design and Optimization of Multi-Modulus-Divider for K-Band Fractional-N Frequency Synthesizer |
|---|---|
| Original language | Chinese (Traditional) |
| Pages (from-to) | 1187-1191 |
| Number of pages | 5 |
| Journal | Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology |
| Volume | 39 |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - 1 Nov 2019 |