TY - GEN
T1 - Analysis of signal and power/ground pin assignment in multi-layer PCB and its impact on signal integrity and crosstalk
AU - Chang, Ka Fai
AU - Cubillo, Joseph Romen
AU - Weerasekera, Roshan
AU - Jin, Cheng
AU - Zheng, Boyu
AU - Bhattacharya, Suryanarayana Shivakumar
PY - 2013
Y1 - 2013
N2 - In this paper, the impact of signal and power/ground pin assignment in multi-layer printed circuit board (PCB) on signal integrity (SI) performance is studied. Efficient return signal current path plays an important role to preserve SI and minimize unwanted crosstalk. Moreover, a high pin count ratio of signal to power/ground is desirable to increase overall system throughput without trading off SI performance. A case study of a 4-layer organic substrate design is demonstrated for SI and power integrity verification. An optimum pattern of signal and power/ground pins in a regular tile pattern is populated over the floorplan to reduce timing skew (2 times improvement) and suppress crosstalk.
AB - In this paper, the impact of signal and power/ground pin assignment in multi-layer printed circuit board (PCB) on signal integrity (SI) performance is studied. Efficient return signal current path plays an important role to preserve SI and minimize unwanted crosstalk. Moreover, a high pin count ratio of signal to power/ground is desirable to increase overall system throughput without trading off SI performance. A case study of a 4-layer organic substrate design is demonstrated for SI and power integrity verification. An optimum pattern of signal and power/ground pins in a regular tile pattern is populated over the floorplan to reduce timing skew (2 times improvement) and suppress crosstalk.
UR - http://www.scopus.com/inward/record.url?scp=84897767549&partnerID=8YFLogxK
U2 - 10.1109/EPTC.2013.6745829
DO - 10.1109/EPTC.2013.6745829
M3 - Conference contribution
AN - SCOPUS:84897767549
SN - 9781479928330
T3 - Proceedings of the 2013 IEEE 15th Electronics Packaging Technology Conference, EPTC 2013
SP - 789
EP - 792
BT - Proceedings of the 2013 IEEE 15th Electronics Packaging Technology Conference, EPTC 2013
T2 - 2013 IEEE 15th Electronics Packaging Technology Conference, EPTC 2013
Y2 - 11 December 2013 through 13 December 2013
ER -