ADC design for neural acquisition application

Ruoyuan Qu; Zhe Guo; Na Liu; Yueyang Chen; Xinghua Wang

doi:10.1007/978-94-007-6516-0_68

ADC design for neural acquisition application

Ruoyuan Qu, Zhe Guo, Na Liu, Yueyang Chen^*, Xinghua Wang

^*Corresponding author for this work

Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A high precision sigma delta analog to digital convertor (SDADC) for neural signal acquisition application is presented in this paper, which has been fabricated in AMI 0.5 um standard CMOS process. The ADC achieves 85 dB SNR in a second older with 256 oversampling rate (OSR) architecture. Behavior level modeling is adopted to shorten the design cycle and provide reference specifications for circuits design. In circuit design, class-AB output structure ensures the enough output range and slew rate of the system requirement. The whole system consumes 0.7 mA current and occupies 0.9*0.5 mm² area.

Original language	English
Title of host publication	Future Information Communication Technology and Applications, ICFICE 2013
Pages	607-614
Number of pages	8
DOIs	https://doi.org/10.1007/978-94-007-6516-0_68
Publication status	Published - 2013
Externally published	Yes
Event	2013 International Conference on Future Information and Communication Engineering, ICFICE 2013 - Shenyang, China Duration: 24 Jun 2013 → 26 Jun 2013

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	235 LNEE
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Conference

Conference	2013 International Conference on Future Information and Communication Engineering, ICFICE 2013
Country/Territory	China
City	Shenyang
Period	24/06/13 → 26/06/13

Keywords

Behavior modeling
Comparator
Integrator
Matlab
Neural acquisition
SDADC

Access to Document

10.1007/978-94-007-6516-0_68

Cite this

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title = "ADC design for neural acquisition application",

abstract = "A high precision sigma delta analog to digital convertor (SDADC) for neural signal acquisition application is presented in this paper, which has been fabricated in AMI 0.5 um standard CMOS process. The ADC achieves 85 dB SNR in a second older with 256 oversampling rate (OSR) architecture. Behavior level modeling is adopted to shorten the design cycle and provide reference specifications for circuits design. In circuit design, class-AB output structure ensures the enough output range and slew rate of the system requirement. The whole system consumes 0.7 mA current and occupies 0.9*0.5 mm2 area.",

keywords = "Behavior modeling, Comparator, Integrator, Matlab, Neural acquisition, SDADC",

author = "Ruoyuan Qu and Zhe Guo and Na Liu and Yueyang Chen and Xinghua Wang",

year = "2013",

doi = "10.1007/978-94-007-6516-0_68",

language = "English",

isbn = "9789400765153",

series = "Lecture Notes in Electrical Engineering",

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booktitle = "Future Information Communication Technology and Applications, ICFICE 2013",

note = "2013 International Conference on Future Information and Communication Engineering, ICFICE 2013 ; Conference date: 24-06-2013 Through 26-06-2013",

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Qu, R, Guo, Z, Liu, N, Chen, Y & Wang, X 2013, ADC design for neural acquisition application. in Future Information Communication Technology and Applications, ICFICE 2013. Lecture Notes in Electrical Engineering, vol. 235 LNEE, pp. 607-614, 2013 International Conference on Future Information and Communication Engineering, ICFICE 2013, Shenyang, China, 24/06/13. https://doi.org/10.1007/978-94-007-6516-0_68

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T1 - ADC design for neural acquisition application

AU - Qu, Ruoyuan

AU - Guo, Zhe

AU - Liu, Na

AU - Chen, Yueyang

AU - Wang, Xinghua

PY - 2013

Y1 - 2013

N2 - A high precision sigma delta analog to digital convertor (SDADC) for neural signal acquisition application is presented in this paper, which has been fabricated in AMI 0.5 um standard CMOS process. The ADC achieves 85 dB SNR in a second older with 256 oversampling rate (OSR) architecture. Behavior level modeling is adopted to shorten the design cycle and provide reference specifications for circuits design. In circuit design, class-AB output structure ensures the enough output range and slew rate of the system requirement. The whole system consumes 0.7 mA current and occupies 0.9*0.5 mm2 area.

AB - A high precision sigma delta analog to digital convertor (SDADC) for neural signal acquisition application is presented in this paper, which has been fabricated in AMI 0.5 um standard CMOS process. The ADC achieves 85 dB SNR in a second older with 256 oversampling rate (OSR) architecture. Behavior level modeling is adopted to shorten the design cycle and provide reference specifications for circuits design. In circuit design, class-AB output structure ensures the enough output range and slew rate of the system requirement. The whole system consumes 0.7 mA current and occupies 0.9*0.5 mm2 area.

KW - Behavior modeling

KW - Comparator

KW - Integrator

KW - Matlab

KW - Neural acquisition

KW - SDADC

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SN - 9789400765153

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BT - Future Information Communication Technology and Applications, ICFICE 2013

T2 - 2013 International Conference on Future Information and Communication Engineering, ICFICE 2013

Y2 - 24 June 2013 through 26 June 2013

ER -

ADC design for neural acquisition application

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Keywords

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